• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.
    公开号:US20010003373A1
    申请号:US09/225,278
    申请日:1999-01-05
    公开日:2001-06-14
    发明作者:Salman Akram
    申请人:Salman Akram；
    IPC主号:H01L23-50
    专利说明:
    [0001] This application is a divisional of application Ser. No. 08/870,614, filed Jun. 6, 1997, pending. [0001] BACKGROUND OF THE INVENTION
    [0002] 1. Field of the Invention [0002]
    [0003] This invention relates in general to chip-on-board applications for integrated circuit dice, and in particular to devices and methods for electrically and thermally coupling to the backsides of dice in such applications. [0003]
    [0004] 2. State of the Art [0004]
    [0005] Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from semiconductor wafers, such as silicon wafers, on which multiple IC's have been fabricated. Most dice are packaged by attaching them to lead frames supported in plastic or ceramic packages, and the lead frames and packages are typically designed to conduct heat away from the dice in order to protect them from heat damage. Such packages are also typically designed to protect the dice from corrosion. [0005]
    [0006] Some dice, however, are packaged in what are known as “chip-on-board” (COB) applications, in which the dice are directly attached to printed circuit boards (PCB's) or other known substrates using well-known die-attach techniques. In these applications, bond pads on one or more dice are connected to signal traces on the surfaces of PCB's or other substrates using wire, or tape-automated, bonding, and a liquid or gel encapsulant, commonly referred to as a “glob top,” is applied over the dice to protect them from corrosion. One such COB application is described in U.S. Pat. No. 5,497,027. [0006]
    [0007] Dice in COB applications typically generate more heat than their associated PCB's alone can satisfactorily conduct away. Consequently, certain techniques have been devised to assist in conducting heat away from dice in COB applications. In one such technique shown in FIG. 1, circuit traces [0007] 10 that widen near a die 12 and are directly attached to the surface 14 of a PCB 16 assist the PCB 16 in conducting significant amounts of heat away from the die 12. Unfortunately, circuit traces that widen sufficiently near dice to satisfactorily conduct heat away from the dice typically use an inordinately large amount of surface space on their associated PCB's. As a result, widened circuit traces can be difficult or impossible to implement in today's densely packed COB applications. Widened circuit traces can also lead to an undesirable increase in capacitive and inductive parasitics, which are highly undesirable for high-speed applications.
    [0008] Another technique for conducting heat away from dice in COB applications involves using thermally conductive PCB's in place of the more commonly used glass-epoxy PCB's. Thermally conductive PCB's are made with materials such as insulated aluminum, porcelainized steel, and ceramics that are superior in heat transfer characteristics than glass-epoxy. Because this technique is not applicable to the glass-epoxy PCB's used in the majority of COB applications, it is of limited utility. [0008]
    [0009] Therefore, there is a need in the art for a device and method for satisfactorily conducting heat away from dice that are directly attached to a variety of PCB's, including conventional, widely-utilized glass-epoxy PCB's, without degrading the electrical characteristics of the interconnecting circuitry in COB applications. [0009] BRIEF SUMMARY OF THE INVENTION
    [0010] An inventive device for chip-on-board applications comprises a base, such as a printed circuit board (PCB) or a multi-chip module, that includes a conductive layer, such as a copper or other metallic plane, positioned on a surface of a supporting insulative substrate. An insulating layer overlies the surface of the conductive layer and defines at least one aperture in substantial registry with a localized region on the conductive layer on which a bare integrated circuit die is to be placed. The backside surface of the die is directly attached to the conductive plane in the localized region using a conductive die-attach material, such as a silver-filled epoxy, interposed between the conductive layer and the die. The inventive device thus can advantageously conduct heat away from the die by directly coupling the backside of the die to the conductive layer through the conductive die-attach material. The device can also conduct a substrate bias voltage to the backside of the die through the conductive layer and the die-attach material. [0010]
    [0011] In a modified version of the base described above, the base includes multiple vertically-separated conductive layers, each layer having a localized region for conductive attachment to one of multiple bare integrated circuit dice. As a result, each of the dice may receive a different substrate bias voltage through its respective conductive layer. [0011]
    [0012] In another embodiment of the present invention, an electronic device includes the base described above and an integrated circuit die, such as a Dynamic Random Access Memory (DRAM) die. In still another embodiment, an electronic system includes input, output, memory, and processor devices, and one or more of these devices includes the base described above. [0012]
    [0013] In a further embodiment, a system for conducting heat away from a die includes a thermally conductive interior PCB layer having a surface with an externally accessible die-attach region. A thermally conductive die-attach material directly attaches a backside surface of the die to the die-attach region to establish thermal conduction between the die and the thermally conductive layer. [0013]
    [0014] In a still further embodiment of the present invention, a system for supplying a substrate bias voltage to a die includes a substrate bias voltage generator and an electrically conductive layer inside a PCB for conducting the substrate bias voltage to an externally accessible die-attach region on the surface of the conductive layer. An electrically conductive die-attach material directly attaches a backside surface of the die to the die-attach region to conduct the substrate bias voltage to the backside surface of the die. [0014] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
    [0015] FIG. 1 is an isometric view of a portion of a prior art printed circuit board that uses widened circuit traces near a directly attached (i.e., “on-board”) integrated circuit die to conduct heat away from the die; [0015]
    [0016] FIG. 2 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to a conductive layer of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between the conductive layer and the dice in accordance with the present invention; [0016]
    [0017] FIG. 3 is an isometric sectional view of the multi-chip module portion of FIG. 2 with an alternative substrate biasing arrangement; [0017]
    [0018] FIG. 4 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to multiple conductive layers of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between each die and one of the conductive layers in accordance with the present invention; and [0018]
    [0019] FIG. 5 is a block diagram of an electronic system including the multi-chip module of FIG. 4. [0019] DETAILED DESCRIPTION OF THE INVENTION
    [0020] As shown in FIG. 2, the present invention comprises a multi-chip module [0020] 20 that includes a plurality of integrated circuit dice 22, each recessed in an aperture 23 in an insulating layer 24 of an insulative base 26. The base 26 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB, the term PCB as employed herein including conductor-carrying substrates of silicon, ceramic, polymers and other materials known in the art. Although the present invention will be described with respect to multi-chip module embodiments, it will be understood by those having skill in the field of this invention that the present invention is also applicable to single-die applications employing PCB's or other conductor-carrying bases. It will also be understood that the present invention is applicable to memory dice, such as Dynamic Random Access Memory (DRAM) dice, packaged in Single In-line Memory Modules (SIMM's), Dual In-line Memory Modules (DIMM's), and memory cards, as well as to processors and other dice commonly employed singly and in multi-chip assemblies on a variety of conductor-carrying substrates.
    [0021] Backsides (not shown) of the dice [0021] 22 are directly attached in a chip-on-board (COB) application to a conductive layer 28 of the base 26 using a conductive die-attach material 30, such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, the conductive layer 28 is positioned on a substrate 32 that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layer may be thermally conductive, electrically conductive, or preferably both, and that the conductive layer may comprise a wide variety of conductive materials, including copper, gold, and platinum. It should also be understood that there may be more than one vertically-superimposed conductive layer in a base and, consequently, that different dice may be attached to different conductive layers in the same base through apertures 23 extending to different depths of base 26.
    [0022] Bond pads [0022] 34 on front- or active-side surfaces of the dice 22 are wire-bonded to signal traces 36 carried on a surface of the insulating layer 24. Of course, the bond pads 34 may also be bonded to the signal traces 36 using tape-automated bonding (TAB) techniques, wherein the conductors are carried on a flexible dielectric film. Also, the signal traces 36 may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. Further, it should be understood that, while the multi-chip module 20 of FIG. 2 is shown as having a single insulating layer 24 between the conductive layer 28 and the signal traces 36, the present invention is equally applicable to COB applications in which there are multiple superimposed layers, such as insulating, conductive, or signal layers, between a conductive layer to which the backside of a die is directly attached and the signal layer to which the front-side of each die is bonded.
    [0023] Because the present invention directly attaches the backsides of dice to a conductive layer, heat from the dice is advantageously conducted away from the dice through the conductive layer. Also, as shown in FIG. 2, a substrate bias voltage generator [0023] 38 can supply a substrate bias voltage Vbb to the backsides (not shown) of the dice 22 through the conductive layer 28. As a result, there is no need for on-board substrate bias voltage generators (not shown) in the dice 22, and there is no need to supply the substrate bias voltage Vbb to the dice 22 through bond pads 34 on their front-side surfaces. Of course, a supply voltage (commonly designated Vcc) ground potential (commonly designated Vss), or electronic signal may be supplied to the dice 22 through the conductive layer 28 in place of the substrate bias voltage Vbb. Also, although the generator 38 is shown in FIG. 2 as applying a negative substrate bias voltage Vbb to the conductive layer 28, it should be understood that the generator 38 may instead provide a positive substrate bias voltage Vbb to the layer 28.
    [0024] The present invention also provides marginally greater physical protection for dice by positioning them within a protective aperture in the thin upper insulating layer [0024] 24. Further, the present invention advantageously allows incrementally shorter bond wires to be used during die-bond because the front-side surfaces of the dice are slightly closer to the level of the signal traces to which they are bonded. While such advantages are relatively small, they are nonetheless significant.
    [0025] As shown in a sectional view in FIG. 3, an alternative version of the multi-chip module [0025] 20 of FIG. 2 includes the substrate bias voltage generator 38 directly applying a bias between the conductive layer 28 and a conductive reference layer 41. Of course, while the reference layer 41 is shown in FIG. 3 as being grounded, it may be coupled to any voltage, particularly other reference voltages.
    [0026] As shown in FIG. 4, the present invention also comprises a multi-chip module [0026] 40 that includes a plurality of integrated circuit dice 42, each recessed in an aperture 43 in insulating layers 44 and 46 and a first conductive layer 48 of an insulative base 50. The base 50 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB.
    [0027] Backsides (not shown) of the dice [0027] 42 are directly respectively attached in a chip-on-board (COB) application to the first conductive layer 48 and a second conductive layer 52 of the base 50 using a conductive die-attach material (not shown), such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, the second conductive layer 52 is positioned on a substrate 54 that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layers may be thermally conductive, electrically conductive, or preferably both, and that the conductive layers may comprise a wide variety of conductive materials, including copper, gold, and platinum.
    [0028] Bond pads [0028] 56 on front- or active-side surfaces of the dice 42 are Tape-Automated Bonded (TAB) to signal traces 58 carried on a surface of the insulating layer 44. Of course, the signal traces may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. The flexible film (usually polyimide) of the TAB tape has been deleted for clarity.
    [0029] Because the present invention directly attaches the backsides of dice to conductive layers, heat from the dice is advantageously conducted away from the dice through the conductive layers. Also, substrate bias voltage generators (not shown) can supply a first substrate bias voltage V[0029] bb1 to the backside (not shown) of one of the dice 42 through the first conductive layer 48 and a second substrate bias voltage Vbb2 to the backside (not shown) of the other of the dice 42 through the second conductive layer 52. As a result, there is no need for on-board substrate bias voltage generators in the dice 42, and there is no need to supply the substrate bias voltages Vbb1 and Vbb2 to the dice 42 through bond pads 56 on their front-side surfaces. Of course, a supply voltage Vcc, ground potential Vss, or electronic signal may be supplied to the dice 42 through the conductive layers 48 and 52 in place of the substrate bias voltages Vbb1 and Vbb2. Also, the substrate bias voltages Vbb1 and Vbb2 can be different voltages.
    [0030] As shown in FIG. 5, the multi-chip module [0030] 40 of FIG. 4 can be incorporated into a memory device 60 of an electronic system 62, such as a computer system, that includes an input device 64 and an output device 66 coupled to a processor device 68. Of course, the multi-chip module 40 can alternatively be incorporated into the input device 64, the output device 66, or the processor device 68. Alternatively, the multi-chip module (not shown) of FIG. 2 may be incorporated into the input device 64, output device 66, processor device 68, or memory device 60. Also, the memory device 60 of FIG. 5 may comprise a DIMM, SIMM, memory card or any other memory die-carrying substrate.
    [0031] Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described. [0031]
    权利要求:
    Claims (43)
    [1" id="US-20010003373-A1-CLM-00001] 1. A printed circuit board for chip-on-board applications, the printed circuit board comprising:
    a first dielectric layer having a surface;
    a conductive layer positioned on the surface of the first dielectric layer and including a die-mounting surface within a chip-attach area of the conductive layer for direct conductive attachment to a backside surface of a bare integrated circuit chip to establish at least one of electrical and thermal conduction between the conductive layer and the chip;
    a second dielectric layer positioned on the conductive layer, the second dielectric layer having an aperture therein to define the chip-attach area of the conductive layer and to receive the bare integrated circuit chip; and
    a layer of signal traces superimposed on the second dielectric layer in a substantially parallel relationship therewith, at least some of the traces including bond pads for electrical connection to a front-side surface of the chip.
    [2" id="US-20010003373-A1-CLM-00002] 2. The printed circuit board of
    claim 1 , wherein the layer of signal traces is positioned on a surface of the second dielectric layer.
    [3" id="US-20010003373-A1-CLM-00003] 3. The printed circuit board of
    claim 1 , wherein a portion of the second dielectric layer aperture extends generally about a periphery of the chip-attach area of the conductive layer.
    [4" id="US-20010003373-A1-CLM-00004] 4. The printed circuit board of
    claim 1 , wherein the signal traces are selected from a group comprising copper, gold, and platinum.
    [5" id="US-20010003373-A1-CLM-00005] 5. A multi-chip module comprising:
    a supporting substrate having an insulative surface;
    a conductive layer positioned on the insulative surface of the supporting substrate and having a surface with a plurality of localized die-attach areas thereon;
    a plurality of bare integrated circuit dice each associated with one of the die-attach areas, each die having opposing front-side and backside surfaces, the front-side surface of each die having a plurality of bond pads thereon;
    a conductive die-attach material interposed between each bare integrated circuit die and its associated die-attach area and directly attaching the backside surface of each die to its associated die-attach area to establish at least one of electrical and thermal conduction between each die and the conductive layer;
    an insulating layer positioned on the surface of the conductive layer, the insulating layer having a plurality of apertures therein, each aperture in substantial registry with one of the attached bare integrated circuit dice;
    a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having a plurality of conductor-devoid areas therein, each conductor-devoid area in substantial registry with one of the attached bare integrated circuit dice, the signal layer including a plurality of terminals; and
    a plurality of conductors coupling the terminals of the signal layer to the bond pads on the front-side surfaces of the bare integrated circuit dice.
    [6" id="US-20010003373-A1-CLM-00006] 6. The multi-chip module of
    claim 5 , wherein the signal layer comprises a plurality of signal traces.
    [7" id="US-20010003373-A1-CLM-00007] 7. The multi-chip module of
    claim 5 , wherein the signal layer terminals comprise bond pads.
    [8" id="US-20010003373-A1-CLM-00008] 8. The multi-chip module of
    claim 5 , wherein at least one of the bare integrated circuit dice comprises a dynamic random access memory die.
    [9" id="US-20010003373-A1-CLM-00009] 9. The multi-chip module of
    claim 5 , wherein the conductive die-attach material comprises a conductive epoxy.
    [10" id="US-20010003373-A1-CLM-00010] 10. The multi-chip module of
    claim 9 , wherein the conductive epoxy comprises a metal filled epoxy.
    [11" id="US-20010003373-A1-CLM-00011] 11. The multi-chip module of
    claim 10 , wherein the metal filled epoxy comprises a silver filled epoxy.
    [12" id="US-20010003373-A1-CLM-00012] 12. The multi-chip module of
    claim 5 , wherein the conductive die-attach material comprises a eutectic material.
    [13" id="US-20010003373-A1-CLM-00013] 13. The multi-chip module of
    claim 12 , wherein the eutectic material comprises a gold and silver eutectic material.
    [14" id="US-20010003373-A1-CLM-00014] 14. The multi-chip module of
    claim 5 , wherein the conductive die-attach material comprises a solder.
    [15" id="US-20010003373-A1-CLM-00015] 15. The multi-chip module of
    claim 5 , wherein the conductive die-attach material comprises a conductive polyamide.
    [16" id="US-20010003373-A1-CLM-00016] 16. The multi-chip module of
    claim 5 , wherein the conductive die-attach material comprises a thermally conductive die-attach material.
    [17" id="US-20010003373-A1-CLM-00017] 17. The multi-chip module of
    claim 5 , wherein the conductors comprise wire bond conductors.
    [18" id="US-20010003373-A1-CLM-00018] 18. The multi-chip module of
    claim 5 , wherein the conductors comprise TAB conductors.
    [19" id="US-20010003373-A1-CLM-00019] 19. An electronic device comprising:
    a supporting substrate having an insulative surface;
    a conductive layer positioned on the insulative surface of the supporting substrate and including a surface with a localized die-attach area thereon;
    a bare integrated circuit die having opposing front-side and backside surfaces, the front-side surface having a plurality of bond pads thereon;
    a conductive die-attach material for directly attaching the backside surface of the bare integrated circuit die to the die-attach area on the surface of the conductive layer to establish at least one of electrical and thermal conduction between the die and the conductive layer;
    an insulating layer positioned on the surface of the conductive layer, the insulating layer having an aperture therein in substantial registry with the attached bare integrated circuit die;
    a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having an aperture therein in substantial registry with the attached bare integrated circuit die, the signal layer including a plurality of terminals; and
    a plurality of conductors coupling the terminals of the signal layer to the bond pads on the front-side surface of the bare integrated circuit die.
    [20" id="US-20010003373-A1-CLM-00020] 20. The electronic device of
    claim 19 , wherein the signal layer comprises a plurality of signal traces.
    [21" id="US-20010003373-A1-CLM-00021] 21. The electronic device of
    claim 19 , wherein the signal layer terminals comprise bond pads.
    [22" id="US-20010003373-A1-CLM-00022] 22. The electronic device of
    claim 19 , wherein the bare integrated circuit die comprises a dynamic random access memory die.
    [23" id="US-20010003373-A1-CLM-00023] 23. The electronic device of
    claim 19 , wherein the conductive die-attach material comprises a conductive epoxy.
    [24" id="US-20010003373-A1-CLM-00024] 24. The electronic device of
    claim 23 , wherein the conductive epoxy comprises a metal-filled epoxy.
    [25" id="US-20010003373-A1-CLM-00025] 25. The electronic device of
    claim 24 , wherein the metal-filled epoxy comprises a silver-filled epoxy.
    [26" id="US-20010003373-A1-CLM-00026] 26. The electronic device of
    claim 19 , wherein the conductive die-attach material comprises a thermally conductive die-attach material.
    [27" id="US-20010003373-A1-CLM-00027] 27. The electronic device of
    claim 19 , wherein the conductors comprise wire bond conductors.
    [28" id="US-20010003373-A1-CLM-00028] 28. The electronic device of
    claim 19 , wherein the conductors comprise tape-automated-bonding conductors.
    [29" id="US-20010003373-A1-CLM-00029] 29. A system for conducting heat away from a bare integrated circuit die, the system comprising:
    a thermally conductive layer positioned internally in a printed circuit board, the thermally conductive layer including a surface with an externally accessible localized die-attach region; and
    a thermally conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the thermally conductive layer to establish thermal conduction between the die and the thermally conductive layer.
    [30" id="US-20010003373-A1-CLM-00030] 30. The system of
    claim 29 , wherein the thermally conductive layer comprises a substantially continuous thermally conductive sheet.
    [31" id="US-20010003373-A1-CLM-00031] 31. The system of
    claim 29 , wherein the thermally conductive layer is also electrically conductive.
    [32" id="US-20010003373-A1-CLM-00032] 32. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system comprising:
    a substrate bias voltage generator for supplying the substrate bias voltage;
    an electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator for conducting the substrate bias voltage, the electrically conductive layer including a surface with an externally accessible localized die-attach region; and
    an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the electrically conductive layer to conduct the substrate bias voltage from the electrically conductive layer to the backside surface of the die.
    [33" id="US-20010003373-A1-CLM-00033] 33. The system of
    claim 32 , wherein the electrically conductive die-attach material comprises a conductive epoxy.
    [34" id="US-20010003373-A1-CLM-00034] 34. The system of
    claim 33 , wherein the conductive epoxy comprises a metal-filled epoxy.
    [35" id="US-20010003373-A1-CLM-00035] 35. The system of
    claim 34 , wherein the metal-filled epoxy comprises a silver-filled epoxy.
    [36" id="US-20010003373-A1-CLM-00036] 36. The system of
    claim 32 , wherein the electrically conductive die-attach material comprises a eutectic material.
    [37" id="US-20010003373-A1-CLM-00037] 37. The system of
    claim 36 , wherein the eutectic material comprises a gold and silver eutectic material.
    [38" id="US-20010003373-A1-CLM-00038] 38. The system of
    claim 32 , wherein the electrically conductive die-attach material comprises a solder.
    [39" id="US-20010003373-A1-CLM-00039] 39. The system of
    claim 32 , wherein the electrically conductive die-attach material comprises a conductive polyamide.
    [40" id="US-20010003373-A1-CLM-00040] 40. The system of
    claim 32 , wherein the electrically conductive die-attach material is also a thermally conductive die-attach material.
    [41" id="US-20010003373-A1-CLM-00041] 41. The system of
    claim 32 , wherein the electrically conductive layer comprises a substantially continuous electrically conductive sheet.
    [42" id="US-20010003373-A1-CLM-00042] 42. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system consisting essentially of:
    a substrate bias voltage generator for supplying the substrate bias voltage;
    an electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator for conducting the substrate bias voltage, the electrically conductive layer including a surface with an externally accessible localized die-attach region; and
    an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the electrically conductive layer to conduct the substrate bias voltage from the electrically conductive layer to the backside surface of the die.
    [43" id="US-20010003373-A1-CLM-00043] 43. A method of making a printed circuit board for supporting a bare integrated circuit die, the method comprising:
    providing a supporting substrate having an insulative surface;
    positioning a conductive layer on the insulative surface of the supporting substrate, the conductive layer having a surface with a localized region for direct conductive attachment to a backside surface of the bare integrated circuit die to establish at least one of electrical and thermal conduction between the conductive layer and the die; and
    positioning an insulating layer on the conductive layer with an aperture in the insulating layer in substantial registry with the localized region on the surface of the conductive layer for receiving the bare integrated circuit die.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6339256B2|2002-01-15|Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications
    US6326696B1|2001-12-04|Electronic package with interconnected chips
    US6534858B2|2003-03-18|Assembly and methods for packaged die on pcb with heat sink encapsulant
    US6707141B2|2004-03-16|Multi-chip module substrate for use with leads-over chip type semiconductor devices
    US7268013B2|2007-09-11|Method of fabricating a semiconductor die package having improved inductance characteristics
    US4996587A|1991-02-26|Integrated semiconductor chip package
    US6831353B2|2004-12-14|Interdigitated leads-over-chip lead frame and device for supporting an integrated circuit die
    US5811879A|1998-09-22|Stacked leads-over-chip multi-chip module
    US6563217B2|2003-05-13|Module assembly for stacked BGA packages
    JPH0846076A|1996-02-16|Packing structure of semiconductor package
    US6294838B1|2001-09-25|Multi-chip stacked package
    US6682954B1|2004-01-27|Method for employing piggyback multiple die #3
    KR100207902B1|1999-07-15|Multi chip package using lead frame
    JP2901401B2|1999-06-07|Multi-chip module
    US20020050378A1|2002-05-02|Double-layered multiple chip module package
    MY127468A|2006-12-29|Metal substrate having an ic chip and carrier mounting
    KR20000052093A|2000-08-16|Multi-chip chip scale package
    US6265769B1|2001-07-24|Double-sided chip mount package
    JPH05315470A|1993-11-26|Multichip module
    JP3036976B2|2000-04-24|Multi-chip module
    JPH11111888A|1999-04-23|Semiconductor module, memory module, electronic device and manufacture of semiconductor module
    JPH0529779A|1993-02-05|Heat-radiating mounting structure for semiconductor
    JPH0662543U|1994-09-02|Hybrid IC device
    同族专利:
    公开号 | 公开日
    US6339256B2|2002-01-15|
    US6299463B1|2001-10-09|
    US6064116A|2000-05-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040212965A1|2003-03-17|2004-10-28|Toshiaki Ishii|Electronic circuit apparatus and method of manufacturing the same|
    US20070216299A1|2006-03-20|2007-09-20|Samsung Electronics Co., Ltd.,|Display device and method of manufacturing the same|
    US20090080279A1|2007-09-25|2009-03-26|Jung Pill Kim|Structure to share internally generated voltages between chips in mcp|
    WO2020041605A1|2018-08-22|2020-02-27|Liquid Wire Inc.|Structures with deformable conductors|US4038488A|1975-05-12|1977-07-26|Cambridge Memories, Inc.|Multilayer ceramic multi-chip, dual in-line packaging assembly|
    US4283755A|1980-02-05|1981-08-11|The United States Of America As Represented By The Secretary Of The Air Force|Modulator multilayer detector|
    JPS6347143B2|1981-06-15|1988-09-20|Fujitsu Ltd||
    US4729061A|1985-04-29|1988-03-01|Advanced Micro Devices, Inc.|Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom|
    JPS6290953A|1985-10-01|1987-04-25|Fujitsu Ltd|Resin-sealed semiconductor device|
    US4992850A|1989-02-15|1991-02-12|Micron Technology, Inc.|Directly bonded simm module|
    FR2653601B1|1989-10-20|1993-10-22|Sgs Thomson Microelectronics Sa|PORTABLE ELECTRONICS CONNECTABLE TO CHIPS.|
    US5138436A|1990-11-16|1992-08-11|Ball Corporation|Interconnect package having means for waveguide transmission of rf signals|
    US5768109A|1991-06-26|1998-06-16|Hughes Electronics|Multi-layer circuit board and semiconductor flip chip connection|
    US5397917A|1993-04-26|1995-03-14|Motorola, Inc.|Semiconductor package capable of spreading heat|
    US5497027A|1993-11-30|1996-03-05|At&T Global Information Solutions Company|Multi-chip module packaging system|
    US5677203A|1993-12-15|1997-10-14|Chip Supply, Inc.|Method for providing known good bare semiconductor die|
    US5467253A|1994-06-30|1995-11-14|Motorola, Inc.|Semiconductor chip package and method of forming|
    US5436203A|1994-07-05|1995-07-25|Motorola, Inc.|Shielded liquid encapsulated semiconductor device and method for making the same|
    US5701032A|1994-10-17|1997-12-23|W. L. Gore & Associates, Inc.|Integrated circuit package|
    US5773195A|1994-12-01|1998-06-30|International Business Machines Corporation|Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap|
    US5844168A|1995-08-01|1998-12-01|Minnesota Mining And Manufacturing Company|Multi-layer interconnect sutructure for ball grid arrays|
    US5672911A|1996-05-30|1997-09-30|Lsi Logic Corporation|Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package|
    US5938956A|1996-09-10|1999-08-17|Micron Technology, Inc.|Circuit and method for heating an adhesive to package or rework a semiconductor die|
    US6064116A|1997-06-06|2000-05-16|Micron Technology, Inc.|Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|US6064116A|1997-06-06|2000-05-16|Micron Technology, Inc.|Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|
    SE513352C2|1998-10-26|2000-08-28|Ericsson Telefon Ab L M|Circuit board and process for making the circuit board|
    US6468638B2|1999-03-16|2002-10-22|Alien Technology Corporation|Web process interconnect in electronic assemblies|
    JP2000315843A|1999-04-30|2000-11-14|Fujitsu Ltd|Printed board and semiconductor device|
    US6359334B1|1999-06-08|2002-03-19|Micron Technology, Inc.|Thermally conductive adhesive tape for semiconductor devices and method using the same|
    WO2001042893A1|1999-12-10|2001-06-14|Hitachi, Ltd|Semiconductor module|
    JP2001351266A|2000-04-06|2001-12-21|Fujitsu Ltd|Optical pickup and optical storage device|
    US6366468B1|2000-04-28|2002-04-02|Hewlett-Packard Company|Self-aligned common carrier|
    US6508595B1|2000-05-11|2003-01-21|International Business Machines Corporation|Assembly of opto-electronic module with improved heat sink|
    US6906411B1|2000-06-29|2005-06-14|Mitsubishi Denki Kabushiki Kaisha|Multilayer substrate module and portable wireless terminal|
    US6788552B1|2000-08-30|2004-09-07|Micron Technology, Inc.|Method and apparatus for reducing substrate bias voltage drop|
    JP2002141463A|2000-10-31|2002-05-17|Mitsubishi Electric Corp|Semiconductor module|
    US6580619B2|2000-11-30|2003-06-17|Intel Corporation|Multilayer reference plane in package devices|
    US6628528B2|2000-11-30|2003-09-30|Theodore Zale Schoenborn|Current sharing in memory packages|
    JP3839267B2|2001-03-08|2006-11-01|株式会社ルネサステクノロジ|Semiconductor device and communication terminal device using the same|
    US6891257B2|2001-03-30|2005-05-10|Fairchild Semiconductor Corporation|Packaging system for die-up connection of a die-down oriented integrated circuit|
    US20040080056A1|2001-03-30|2004-04-29|Lim David Chong Sook|Packaging system for die-up connection of a die-down oriented integrated circuit|
    US6761978B2|2001-04-11|2004-07-13|Xerox Corporation|Polyamide and conductive filler adhesive|
    US6532162B2|2001-05-26|2003-03-11|Intel Corporation|Reference plane of integrated circuit packages|
    US6606247B2|2001-05-31|2003-08-12|Alien Technology Corporation|Multi-feature-size electronic structures|
    US20050178884A1|2001-11-06|2005-08-18|Konrad Schafroth|Flight device with a lift-generating fuselage|
    JP2003188262A|2001-12-14|2003-07-04|Mitsubishi Electric Corp|Semiconductor element|
    US7214569B2|2002-01-23|2007-05-08|Alien Technology Corporation|Apparatus incorporating small-feature-size and large-feature-size components and method for making same|
    US7548430B1|2002-05-01|2009-06-16|Amkor Technology, Inc.|Buildup dielectric and metallization process and semiconductor package|
    US11081370B2|2004-03-23|2021-08-03|Amkor Technology Singapore Holding Pte. Ltd.|Methods of manufacturing an encapsulated semiconductor device|
    EP1505582A4|2002-05-15|2007-09-19|Matsushita Electric Ind Co Ltd|Optical head|
    US7253735B2|2003-03-24|2007-08-07|Alien Technology Corporation|RFID tags and processes for producing RFID tags|
    US6768386B1|2003-04-22|2004-07-27|Lsi Logic Corporation|Dual clock package option|
    US6791177B1|2003-05-12|2004-09-14|Lsi Logic Corporation|Integrated circuit packaging that uses guard conductors to isolate noise-sensitive signals within the package substrate|
    JP3734807B2|2003-05-19|2006-01-11|Ｔｄｋ株式会社|Electronic component module|
    JP4049112B2|2004-03-09|2008-02-20|株式会社日立製作所|Electronic equipment|
    US20050245062A1|2004-04-29|2005-11-03|Jeff Kingsbury|Single row bond pad arrangement|
    KR100548582B1|2004-07-23|2006-02-02|주식회사 하이닉스반도체|pad part of semiconductor device|
    US7551141B1|2004-11-08|2009-06-23|Alien Technology Corporation|RFID strap capacitively coupled and method of making same|
    US7353598B2|2004-11-08|2008-04-08|Alien Technology Corporation|Assembly comprising functional devices and method of making same|
    US7452748B1|2004-11-08|2008-11-18|Alien Technology Corporation|Strap assembly comprising functional block deposited therein and method of making same|
    US7688206B2|2004-11-22|2010-03-30|Alien Technology Corporation|Radio frequency identificationtag for an item having a conductive layer included or attached|
    US20060109130A1|2004-11-22|2006-05-25|Hattick John B|Radio frequency identificationtag for an item having a conductive layer included or attached|
    US7385284B2|2004-11-22|2008-06-10|Alien Technology Corporation|Transponder incorporated into an electronic device|
    US8077478B2|2005-03-17|2011-12-13|Panasonic Corporation|Module board|
    CN100411125C|2005-05-30|2008-08-13|矽品精密工业股份有限公司|Method for preparing packages of semiconductor, and cutting unit|
    US7542301B1|2005-06-22|2009-06-02|Alien Technology Corporation|Creating recessed regions in a substrate and assemblies having such recessed regions|
    US7198988B1|2005-11-16|2007-04-03|Emcore Corporation|Method for eliminating backside metal peeling during die separation|
    US20090268513A1|2008-04-29|2009-10-29|Luca De Ambroggi|Memory device with different types of phase change memory|
    FR2976403B1|2011-06-09|2013-11-22|St Microelectronics Rousset|METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT WITHOUT MASS CONTACT RANGE|
    US8698291B2|2011-12-15|2014-04-15|Freescale Semiconductor, Inc.|Packaged leadless semiconductor device|
    US8803302B2|2012-05-31|2014-08-12|Freescale Semiconductor, Inc.|System, method and apparatus for leadless surface mounted semiconductor package|
    DE102012107668A1|2012-08-21|2014-03-20|Epcos Ag|component assembly|
    US20140199904A1|2013-01-31|2014-07-17|Laird Technologies, Inc.|Electrically Conductive Porous Material Assemblies and Methods of Making The Same|
    US9258878B2|2013-02-13|2016-02-09|Gerald Ho Kim|Isolation of thermal ground for multiple heat-generating devices on a substrate|
    US9508635B2|2013-06-27|2016-11-29|STATS ChipPAC Pte. Ltd.|Methods of forming conductive jumper traces|
    WO2015142428A1|2014-03-18|2015-09-24|Labinal, Llc|Backplane module and method of manufacturing same|
    USD760230S1|2014-09-16|2016-06-28|Daishinku Corporation|Piezoelectric vibration device|
    法律状态:
    2005-06-21| FPAY| Fee payment|Year of fee payment: 4 |
    2007-09-18| CC| Certificate of correction|
    2009-06-17| FPAY| Fee payment|Year of fee payment: 8 |
    2013-08-23| REMI| Maintenance fee reminder mailed|
    2014-01-15| LAPS| Lapse for failure to pay maintenance fees|
    2014-02-10| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2014-03-04| FP| Expired due to failure to pay maintenance fee|Effective date: 20140115 |
    优先权:
    申请号 | 申请日 | 专利标题
    US08/870,614|US6064116A|1997-06-06|1997-06-06|Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|
    US09/225,278|US6339256B2|1997-06-06|1999-01-05|Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|US09/225,278| US6339256B2|1997-06-06|1999-01-05|Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|
    US09/652,407| US6299463B1|1997-06-06|2000-08-31|Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications|
    [返回顶部]